As is commonly known and appreciated, integrated circuits are commonly fabricated using one or more process steps. Such process steps are often executed in lots. The lots commonly contain multiple wafers, with each wafer containing multiple integrated circuits. Commonly, individual integrated circuits can be identified during fabrication based on their position on a wafer, for a given lot. Commonly an X-Y coordinate system is used for identifying the portion of the wafer, the portion often being referred to as an integrated circuit. Such coordinate system can be used during fabrication and before cutting of the wafer into individual integrated circuits. For example, a given integrated circuit may be fabricated in lot “Q,” on wafer “N,” at X-coordinate “A” and Y-coordinate “B.” Where each of Q, N, A and B are real numbers. Accordingly, during the fabrication process, the identification of individual integrated circuits can commonly be accomplished using a lot/wafer/integrated circuit identification scheme. Such identification scheme permits tracking of each integrated circuit, during fabrication, in a database or otherwise. However, during fabrication each wafer is eventually cut into separate integrated circuits, packaged, and then utilized as desired. The packaging for the integrated circuit commonly identifies the lot in which it was fabricated, but, does not identify the wafer or location thereon. Upon a wafer being cut and packaged, the traceability of a given integrated circuit can no longer be made simply based upon the lot/wafer/integrated circuit identification scheme. Instead, an additional identifier is commonly needed.
Further, integrated circuits are often fabricated in high volumes and used in applications where quality is vitally important. Examples of such applications include, but are not limited to, automotive electronics. While significant process controls are used to prevent and minimize the occurrence of defects during the fabrication of integrated circuits, due to the substantial number of circuits often fabricated, even rare problems, such as those measured in parts per million (ppm) and/or parts per billion (ppb) can be troublesome. Such concerns are further enhanced by the substantial number of such circuits utilized in automobiles and other implementations. Such uses often number in the hundreds of circuits per any given vehicle or other implementation. Given the volumes involved, such errors may result in substantial business, economic and other pressures being exerted on fabricators of such circuits. These concerns commonly result in increased efforts by fabricators, when defects do arise, to determine the root cause of the failure in order to satisfy a zero defects standard.
Yet, determining the root cause of a defect in an integrated circuit is inherently difficult. This difficulty is often due, at least in part, to a large number of possible failure modes which originate from the combination of a complex fabrication process with a complex circuit design. Additionally, to determine whether a solution actually overcomes a defect often results in substantial costs to manufacturers in terms of long cycles for improvements and a need to use numerous engineers to, as best as possible, definitively identify and implement corrective actions to prevent defects in integrated circuits. Therefore it is of major importance to have as much information as possible about the defective integrated circuit. If the integrated circuit is uniquely identifiable it becomes possible to access any previously stored information about the integrated circuit. This information can be used to apply statistical post-processing techniques, such as Part Average Testing, which is a commonly known method to detect and remove statistical outliers during production testing.
Notably, numerous approaches have been proposed for uniquely identifying integrated circuits. These approaches have included the use of marks or designators on integrated circuits, packaging, or otherwise. Examples of such approaches are disclosed in Patent and/or Patent Application Publication Numbers US2017/0243831, US2003/0062609, EP2625708, US2016/0351508, US2005/0042780, US2014/0061952 and otherwise. Other approaches have included the use of additional circuit components such as memory components, certain discrete components such as resistors and capacitors, or non-discrete components such as transistors. Examples of such approaches are disclosed in Patent and/or Patent Application Publication Numbers U.S. Pat. Nos. 6,161,213, 6,941,536, US2004/0124437, US2004/0006404, and otherwise. Each of these known approaches, however, are insufficient for a variety of reasons including requiring additional process steps, requiring use of additional and substantial die space to provide the components used for die level tracing, providing only partial traceability, the identifier utilized being subject to tampering, change or copying, requiring the use of dedicated test equipment to trace a given integrated circuit, requiring the use of digital identifiers, and otherwise.
Accordingly, a need exists for providing die level traceability using natural process variations that arise during fabrication of integrated circuits, where such traceability does not require the use of additional process steps, or substantial die space, are tamper proof, and can be detected using commonly available test equipment and processes. Such needs are addressed by one or more of the embodiments of the present disclosure.